1. Field
The following description relates to a coarse-grained reconfigurable processor and a code decompression method thereof, and more particularly, to a coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof.
2. Description of the Related Art
Code compression of a processor is advantageous in that a memory capacity and power consumption may be reduced in a processor chip.
The code compression is roughly divided into a statistical scheme and a dictionary scheme.
The statistical scheme is a scheme of assigning a short codeword to a frequently used code. The statistical scheme is advantageous in that a high compression rate is provided for a code of which a use frequency is high, but is disadvantageous in that parallel decompression is difficult.
The dictionary scheme uses an index of a dictionary as a codeword after the dictionary storing a plurality of codes within a memory of a processor is prepared. The dictionary scheme is advantageous in that random access and parallel decompression are easy because a length of the codeword may be fixed. However, there is a disadvantage in that compression efficiency is low when a size of the dictionary increases due to an increasing number of stored codes and a complex overflow should be processed to use a code unregistered in the dictionary when a size of the dictionary is reduced.
On the other hand, a coarse-grained reconfigurable processor (coarse-grained reconfigurable array (CGRA)) is hardware having an array of a plurality of function units (FUs) capable of rapidly processing a large-scale function.
Because the degradation of performance is serious when the coarse-grained reconfigurable processor does not fetch a code for every cycle, a code is generally stored in a near on-chip memory, that is, a configuration memory. However, because the number of FUs is large in the coarse-grained reconfigurable processor, a code length necessary to process a function is also very long.
Accordingly, there is a problem in that the on-chip memory excessively occupies an area on a coarse-grained reconfigurable processor chip and excessively consumes power when appropriate code compression is not performed.